A connective in logic which yields true if any one of a sequence conditions is true, and false if all conditions are false. In formal logic, the term disjunction (or, more specifically, inclusive disjunction) is commonly used to describe the OR operator. OR is denoted (Mendelson 1997, p. 13), , (Simpson 1987, p. 539), or (Simpson 1987, p. 539). The circuit diagram symbol for an OR gate is illustrated above.
The symbol derives from the first letter of the Latin word "vel," meaning "or," and the expression is voiced either " or " or " vel ." The way to distinguish the similar symbols (AND) and (OR) is to note that the symbol for AND is oriented in the same direction as the capital letter 'A." The OR operation is implemented in the Wolfram Language as Or[A, B, ...].
(Mendelson 1997, p. 26).
A product of ORs is called a disjunction and is denoted
For example, the truth table for the ternary OR operator is shown below (Simpson 1987, p. 543).
A bitwise version of OR can also be defined that performs a bitwise OR on the binary digits of two numbers and and then converts the resulting binary number back to decimal. Bitwise OR is sometimes denoted and is implemented in the Wolfram Language as BitOr[n1, n2, ...]. The illustration above plots the bitwise OR of the array of numbers from to 31 (Wolfram 2002, p. 871).